1. Field of the Invention
The present invention relates to a waveform shaping device for converting the duty ratio, the frequency and the like of a clock signal, and to a clock supply apparatus formed by combining a DLL device with the waveform shaping device.
2. Description of the Background Art
A DLL (Delay Locked Loop) device causes a variable delay circuit to delay an external clock by a time which does not quite reach a 1-clock cycle, and offsets delays generated by a clock driver and the like so as to supply an internal clock with substantially same phase as that of the external clock. The DLL device operates by adding a delay which is a little smaller than the 1-clock cycle to the delays generated by the clock driver and the like so as to get the delay of exact 1-clock cycle. For this reason, it seems as if the internal clock is supplied without any delay.
FIG. 47 is a block diagram showing the structure of a clock supply apparatus using the DLL device according to the prior art which is the background of the present invention. In FIG. 47, the reference numeral 1 designates a DLL device, the reference numeral 3 designates a clock driver, the reference numeral 4 designates a clock wiring, the reference numeral 6 designates a clock input terminal, the reference numeral 201 designates a variable delay circuit, the reference numeral 202 designates a phase comparator, the reference numeral 203 designates a charging pump circuit, the reference numeral 204 designates a loop filter, the reference numeral 551 designates a clock supply apparatus, CL designates an input clock (external clock), OUT.sub.-- D designates an output clock, Vc designates a control signal, and FB designates a feedback clock.
A device portion for receiving the supply of a clock through the clock wiring 4 is usually integrated into a single semiconductor chip. Similarly, the DLL device 1 and the clock driver 3 are usually built in the same semiconductor chip.
FIG. 48 is a circuit diagram showing an example of the well-known structure of the phase comparator 202 according to the prior art. In this example, a Motorola type phase frequency comparator is used. In FIG. 48, N1 to N9 designate NAND circuits, Q1 to Q4 designate output signals of an SR flip-flop formed by the NAND circuits N1 to N8, UP* designates an up signal, DWN* designates a down signal, and RESET* designates a reset signal.
FIG. 49 is a timing chart showing the signal waveform of each portion which accompanies the operation of the device shown in FIG. 48. As shown in FIG. 49, if the phase of the feedback clock FB is later than that of the input clock CL, the up signal UP* becomes an active value (In this case, a value is "0") over a period which is equivalent to a phase difference. On the contrary, if the phase of the feedback clock FB is earlier than that of the input clock CL, the down signal DWN* becomes active over a period which is equivalent to a phase difference.
FIG. 50 is a state transition diagram of the device shown in FIG. 48. As shown in FIG. 50, when the input clock CL rises in the idle state in which neither the up signal UP* nor the down signal DWN* is outputted, the up signal UP* becomes active. Then, when the feedback clock FB rises, reset is performed to return to the idle state. When the feedback clock FB rises earlier, the down signal DWN* becomes active.
FIG. 51 is a circuit diagram showing an example of the well-known structures of the charging pump circuit 203 and the loop filter 204 according to the prior art. In FIG. 51, the reference numerals 211 and 212 designate current sources, the reference numeral 213 designates a PMOS transistor, the reference numeral 214 designates an NMOS transistor, the reference numeral 215 designates an inverter, the reference numeral 216 designates a capacity element, the reference numeral 217 designates a resistive element, Icp1 designates a current supplied from the current source 211, and Icp2 designates a current supplied from the current source 212.
FIG. 52 is a circuit diagram showing the structure of the current source 211. In FIG. 52, the reference numeral 221 designates a PMOS transistor, and the reference numeral 222 designates a bias source for supplying a bias voltage to the PMOS transistor 221.
FIG. 53 is a circuit diagram showing the structure of the current source 212. In FIG. 53, the reference numeral 223 designates an NMOS transistor, and the reference numeral 224 designates a bias source for supplying a bias voltage to the NMOS transistor 223. The bias voltages are supplied from the bias sources 222 and 224 in such a manner that the currents Icp1 and Icp2 are equal to each other.
With reference to FIG. 51 again, when the up signal UP* is active, the PMOS transistor 213 is turned on and the current Icp1 supplied from the current source 211 is fed to the loop filter 204 to charge the capacity element 216. On the contrary, when the down signal DWN* is active, the NMOS transistor 214 is turned on and the capacity element 216 is discharged by the current Icp2 supplied from the current source 212.
More specifically, the charging pump circuit 203 supplies the currents Icp1 and Icp2 set by the current sources 211 and 212 to the loop filter 204 in mutually opposite directions over a period where the up signal UP* and the down signal DWN* are active, which is referred to as a current packet. Positive and negative current packets are stored by the capacity element 216 which is provided in the loop filter 204. FIG. 54 is a circuit diagram showing an example of the well-known structure of a variable delay circuit 201 according to the prior art. In FIG. 54, the reference numeral 232 designates a resistive element, the reference numerals 233, 235 and 243 designate NMOS transistors, the reference numerals 234, 236 and 244 designate PMOS transistors, and the reference numeral 245 designates an inverter. The input clock CL is inputted to a first stage of the inverters 245 which are cascade-connected, and the output clock OUT.sub.-- D is outputted from a final stage. Every time the input clock CL is propagated to each stage of the inverter 245, a delay time is accumulated.
A current which flows in the resistive element 232 is regulated by the control signal Vc. The magnitude of the current is reflected in that of a current which flows in the MOS transistors 243 and 244 by current mirror circuits which are formed by the PMOS transistors 234 and 236 and the NMOS transistors 235 and 243 respectively. The MOS transistors 243 and 244 function as the current sources of the inverters 245.
More specifically, the source current of each inverter 245 is regulated by the control signal Vc. As the voltage of the control signal Vc is higher, the source current is increased. As the magnitude of the current supplied to the inverter 245 is increased, the delay time of the clock which passes through the inverter 245 is reduced. In other words, as the voltage of the control signal Vc is higher, the delay quantity of the output clock OUT.sub.-- D for the input clock CL is reduced.
With reference to FIG. 47 again, the input clock CL sent through the clock input terminal 6 is delayed by the DLL device 1 and outputted as the output clock OUT.sub.-- D. The output clock OUT.sub.-- D is amplified by the clock driver 3 and then transferred to the clock wiring 4.
The clock wiring 4 usually has the form of a clock tree. A clock on the intermediate skew point of the clock tree is picked up as the feedback clock FB and fed back to the phase comparator 202 of the DLL device 1.
When the phase of the feedback clock FB is later than that of the input clock CL, the phase comparator 202 outputs the up signal UP* over a period which is equivalent to a phase difference for each cycle of the input clock CL. Accordingly, the charging pump circuit 203 sends the positive current packet to the loop filter 204. As a result, the control signal Vc outputted from the loop filter 204 is raised. Consequently, the delay quantity of the variable delay circuit 201 is decreased so that the phase of the output clock OUT.sub.-- D is advanced and the phase of the feedback clock FB approaches that of the input clock CL.
On the contrary, when the phase of the feedback clock FB is earlier than that of the input clock CL, the phase comparator 202 outputs the down signal DWN* over a period which is equivalent to a phase difference for each cycle of the input clock CL. Accordingly, the charging pump circuit 203 sends the negative current packet to the loop filter 204. As a result, the control signal Vc outputted from the loop filter 204 drops. Consequently, the delay quantity of the variable delay circuit 201 is increased so that the phase of the output clock OUT.sub.-- D is delayed and the phase of the feedback clock FB approaches that of the input clock CL.
When the phase of the feedback clock FB is coincident with that of the input clock CL, the phase comparator 202 outputs neither the up signal UP* nor the down signal DWN* so that the supply of the current packet to the loop filter 204 is stopped. Consequently, the control signal Vc is not changed. Accordingly, the phase of the feedback clock FB gradually converges on that of the input clock CL so that the phase difference becomes stable in the zero state. The coincidence of the phases is apparent or substantial one. To be exact, the phase of the feedback clock FB is delayed by one cycle of the input clock CL. However, such apparent coincidence is practically equivalent to no phase difference.
As described above, the clock supply apparatus comprising the DLL device according to the prior art functions to compensate for the delay time of a clock. For a duty ratio related to the waveform of the clock, the value of the input clock CL is transmitted to the clock wiring 4 as it is. There is a case where some of various device portions for receiving the supply of the clock through the clock wiring 4 operate at the leading edge of the clock and some of them operate at the trailing edge of the clock. In this case, it is preferable that the duty ratio of the clock should be 50%. By way of example, an edge-triggered flip-flop and a macro block such as a RAM (a circuit block which has a very large hardware scale and implements the specific functions, for example, a RAM, a FIFO, an ALU and the like) are provided together.
If the device portion in which the operation that is started at the leading edge of the clock is latched at the trailing edge of the clock and the device portion which performs the reverse operation are provided together, it is assumed that the duty ratio of the supplied clock is 30%. While the operation should be terminated in a time which is 30% of the clock cycle in the former device portion, the operation can be performed in a time which is 70% of the clock cycle in the latter device portion.
If the amounts of operation of both device portions are equal to each other, the maximum operating speed of the whole apparatus is determined by a period in which the clock has a value of "1" (HIGH level), that is, a length which is 30% of the cycle. On the other hand, if the duty ratio of the clock is 50%, it is possible to employ a higher clock frequency than in the case where the duty ratio of the clock is 30%. In other words, the whole apparatus can operate at a higher speed. Accordingly, it is desirable that the clock supply apparatus comprising the DLL device should have the waveform shaping function for converting the duty ratio of the clock to 50%.
It is not easy to become conscious of the operation performed for a period in which the clock has a value of "1" and the operation performed for a period in which the clock has a value of "0" (LOW level) to be positively reflected in design for each device portion. For this reason, the largest margin of design can usually be obtained by employing the clock having a duty ratio of 50% described above. Assuming that the circuit can operate at the highest speed when the duty ratio of the clock is set to a specific value other than 50%, however, the operating speed of the circuit can be increased to the maximum of potential capacities if the clock supply apparatus can give a desired duty ratio irrespective of the duty ratio of the clock supplied from the outside of the circuit.
Some apparatus need clocks having different phases for each device portion, and some apparatus need clocks having different frequencies for each device portion. However, a clock supply apparatus having the waveform shaping function for converting the duty ratio, the frequency, the number of phases and the like of the clock supplied from the outside has not been known as an apparatus having the function of compensating for out-of-phase according to the prior art.